In transistor technology, several parameters and combinations thereof play an important role in determining the applicability range and transistor speed, which have to be combined with size and semiconductor integration requirements of micro- and nanoelectronics. For example, the current that the transistor allows to flow when the transistor is in on-state (ON-current ION) is an important factor for applicability. Similarly, the OFF-current IOFF should be low in low-power applications. The difference in gate voltage which needs to be applied in order to obtain a decade of change in current flowing through the transistor as it switches from the off- to the on-state is a parameter called subthreshold swing (SS). The lower the average SS value, the faster a transistor can reach the ON-current ION. In traditional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) at room temperature, this SS is limited to 60 mV/decade at room temperature due to the thermal energy of the carriers and the capacitance of the transistors.
On the other hand, Tunnel Field-Effect transistors use band-to-band tunneling (BTBT), a process in which electrons tunnel from the valence band through the semiconductor bandgap to the conduction band or vice versa. Transistors operating under BTBT can reach lower SS values, but often at the cost of a lower ON-current. Such Tunnel FETs (TFETs) comprise a particular doping profile and connections defining a source region, a gate, a channel and a drain region. Source and drain regions are doped regions with opposite doping types. The drain doping determines the type of TFET, so for example n-TFETs comprise drains with n-type doping. The SS value and ON-current has been improved by improving doping levels and by choosing appropriate materials. For example, IV materials as well as mixtures of III-V materials have been implemented in TFETs, but the optimization of both SS and ON-currents is challenging. An additional important factor is the OFF-current, which should be low. Gate-drain underlap and reduced drain doping, as well as using a material with wide bandgap in the drain, are used to reduce OFF-current. Unfortunately, the gate-drain underlap and the reduced drain doping concentration limit the maximum current through the TFET. The requirement of low OFF-current is in conflict with the requirement of a sufficiently high ON-current.